#include "gd32h7xx.h"
void BOARD_ConfigMPU(void)
{
    /* Disable I cache and D cache */
    if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
    {
        SCB_DisableICache();
    }
    if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
    {
        SCB_DisableDCache();
    }
    
    /* Disable MPU */
    ARM_MPU_Disable();
    
    /* Region 0 setting: Instruction access disabled, No data access permission. */
    MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
    MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);

    /* Region 1 SDRAM*/
    MPU->RBAR = ARM_MPU_RBAR(1, 0xC0000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_32MB);
    
    /* Region 2 FLASH PART 1*/
    MPU->RBAR = ARM_MPU_RBAR(2, 0x08000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_2MB);
    
    /* Region 3 FLASH PART 2 */
    MPU->RBAR = ARM_MPU_RBAR(3, 0x08200000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
    
    /* Region 4 FLASH PART 3 */
    MPU->RBAR = ARM_MPU_RBAR(4, 0x08300000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
    
    /* Region 5 FLASH PART 4*/
    MPU->RBAR = ARM_MPU_RBAR(5, 0x08380000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
    
    /* Region 6 SRAM PART 1*/
    MPU->RBAR = ARM_MPU_RBAR(6, 0x24000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
    
    /* Region 7 SRAM PART 2*/
    MPU->RBAR = ARM_MPU_RBAR(7, 0x24080000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
    
    /* Region 8 SRAM PART 3*/
    MPU->RBAR = ARM_MPU_RBAR(8, 0x240C0000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
    
    /* Region 9 */
    MPU->RBAR = ARM_MPU_RBAR(9, 0x40000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
    
    MPU->RBAR = ARM_MPU_RBAR(10, 0xC1E00000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
    
    /* Enable MPU */
    ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
    
    /* enable i-Cache */
    SCB_EnableICache();

    /* enable d-Cache */
    SCB_EnableDCache();
}